AT91SAM9260产品描述
AT91SAM9260是首款与基于ARM9的微控制器系列产品针脚兼容的产品。基于ARM9的微控制器系列产品正如基于ARM7的控制器一样，拥有相同的编程模型，这使得在基于不同ARM核心的控制器之间可以进行直接移植。 本产品支持决定性的、实时的操作，提供监管功能，与8位微控制器相比还获得了第三方的支持。
AT91SAM9260基于ARM926EJ-S处理器，具备8KB指令以及8KB数据缓存。 在190 MHz时钟频率下运行时性能可达210 MIPS。 该产品包含了8KB SRAM以及32KB ROM，在最高处理器或总线速度下可实现单周期访问。该产品还具备外部总线接口，这些外部总线接口中包含了诸多控制器，用于控制SDRAM以及包括NAND Flash和CompactFlash在内的静态存储器。 其广泛的外围设备集包括USB全速主机和设备接口、10/100 Base T以太网MAC、图像传感器接口、多媒体卡接口（MCI）、同步串行控制器（SSC）、USART、主/从串行外围设备接口（SPI）、一个三通道16位定时计数器（TC）、一个双线接口（TWI）以及四通道10位模数转换器。 三个32位并行输入/输出控制器让针脚可以与这些外围设备实现多路复用，从而减少了设备的针脚数量以及外围设备DMA通道，将接口与片上、片外存储器之间的数据吞吐量提升到了最高水平。
AT91SAM9260拥有可实现高效系统管理的全功能系统控制器，其中包含了一个复位控制器、关机控制器、时钟管理、高级中断控制器（AIC）、调试单元（DBGU）、周期间隔定时器、看门狗定时器以及实时定时器。 本产品有符合RoHS标准的217球LFBGA封装以及208针绿色QFP封装两种版本。 AT91SAM9260评估板以及广泛的第三方应用程序开发工具均支持AT91SAM9260。 本产品支持Linux以及Windows CE。 本产品专为高度互联的图像处理应用而开发，例如销售点终端、基于以太网的IP摄像头以及条形码读出器等等。
描述AT91SAM9260
这个AT91SAM9260是第一个成员的一个pin-compatible ARM9-based单片机家庭共享同一个编程模型ARM7-based控制器,允许直接移民基于不同臂芯控制器。它支持的确定性、实时性、提供管理职能,并具有相当的第三方支持8位微控制器。
这个AT91SAM9260是基于处理器的ARM926EJ-S,8K字节指令和数据缓存的记忆。8K字节它在210印迹有190兆赫的时钟。它的特性和32K 8K字节的内存和单周期字节的存储器存取到最大处理器或汽车速度,连同外部总线接口和控制器的SDRAM和静态的记忆,包括NAND闪存和CompactFlash。其广泛的周边包括USB全速主持人和设备接口,麦克,23基T以太网图像传感器界面、多媒体卡接口(MCI)、同步串行控制器(SSC),USARTs、主/奴隶串行外围接口(共),一个三通道16个定时器柜台(TC),一个两线接口(双胞胎)和4通道成功。三32位的平行的I / O控制器的杆/从这些外设为了减少
AT91SAM9260特性
DSP指令延伸,手臂,Jazelle?技术对Java?加速度
数据缓存,8-KByte——8-KByte指令缓存写缓冲
在180印迹- 200兆赫
-内存管理单元
EmbeddedICE &# 8482;、调试,通信信道的支持
额外的嵌入式的记忆
32 KByte——Single-cycle内部存储器,能在最高转速。矩阵
4 KByte - 2,Single-cycle内部静态存储器存取到最大矩阵的速度
外部总线接口(埃比)。
SDRAM,静态存储器——支持,ECC-enabled NAND闪存和CompactFlash?
USB 2.0全速(12 Mbits)装置的港口
2,432-byte——以收发器、综合DPRAM 220821号
USB 2.0全速(12 Mbits)举办的208-lead PQFP单港口
包装和双港LFBGA 217-ball包裹
-单或双片上接收器
综合FIFOs和献身精神,直接存储器存取隧道
23基。”麦克以太网
媒体独立的接口或者减少,媒体独立的接口
28-byte FIFOs和献身精神,直接存储器存取隧道为收发
图像传感器的接口
ITU-R BT。601/656——外部接口,可编程框架捕捉速率
12-bit数据接口,支持高敏感性的传感器
EAV同步——SAV和路径与计数器,YCbCr预览格式
公共汽车矩阵,
- 6 32-bit-layer矩阵
启动方式选择选项,——Remap命令
Fully-featured系统控制器,包括
-重置控制器,关机控制器
四32位的电池备份注册为共有16个字节
时钟发生器和电源管理,控制器
中断控制器和调试-先进单位
周期间隔计时器——看门狗定时器和即时计时器 重置控制器(开发)。
Power-on -基于细胞来源,重新复位鉴定和复位输出
控制
时钟发生器(CKGR)。
32,768赫兹低能振荡器,选择或内部低功率RC振荡器
电池备用电源,提供一个永久的缓慢的时钟
20兆赫兹- 3片上振荡器,一起来240兆赫锁和一个1.3兆赫锁
电源管理器(PMC)。
-非常缓慢的时钟操作方式、软件编程功率最优化
能力,
可编程的外部时钟信号——两种
先进的中断控制器(工商局)。
Maskable优先,Eight-level——独立、矢量中断源
- 3外部中断源和一个快速中断源、伪造的
中断的保护。
调试单元(DBGU)。
- 2线UART和支持调试通信通道,可防止冰访问
周期间隔计时器(井)。
20-bit间隔计时器加上12-bit——间隔柜台
看门狗定时器(WDT)。
只有一次,可Key-protected—16位计数器运行时,被缓慢的时钟
即时计时器内河货运码头)。
- 32位Free-running备份柜台运行在缓慢的时钟和16分频器
一个4-channel成功模拟数字的变换器
三32位的平行的输入/输出控制器(PIOA PIOB,PIOC),
96 -可编程的I / O线多路复用和两个周边的I / O操作系统
输入变化的能力,在每一个中断I / O线
个人可编程端-拉电阻器及同步输出,
-支大电流驱动I / O线,多达16个马
周边的直接存储器存取控制器通道(PDC)。
一个Two-slot多媒体卡接口(MCI)。
SDCard / SDIO和MultiMediaCard—— &# 8482;兼容
——自动控制,快速自动数据协议转让与PDC)
一个同步串行控制器(SSC)。
独立的时钟和帧同步——每个收发讯号
——我平方米的模拟接口支持、时分多路复用的支持
高速连续的数据流的能力,和32位式的 AT91SAM9260 描述
The AT91SAM9260 is the first member of a pin-compatible ARM9-based microcontroller family that shares the same programming model as ARM7-based controllers, allowing direct migration between controllers based on different ARM cores. It supports deterministic, real-time operation, offers supervisory functions, and has third-party support comparable to that for 8-bit microcontrollers.
The AT91SAM9260 is based on the ARM926EJ-S processor, with 8K byte instruction and 8K byte data cache memories. It operates at 210 MIPS with a 190 MHz clock. It features 8K bytes of SRAM and 32K bytes of ROM with single cycle access at maximum processor or bus speed, together with an external bus interface with controllers for SDRAM and static memories including NAND Flash and CompactFlash. Its extensive peripheral set includes USB Full Speed Host and Device interfaces, a 10/100 Base T Ethernet MAC, Image Sensor Interface, Multimedia Card Interface (MCI), Synchronous Serial Controllers (SSC), USARTs, Master/Slave Serial Peripheral Interfaces (SPI), a three-channel 16-bit Timer Counter (TC), a Two Wire Interface (TWI) and four-channel 10-bit ADC. Three 32-bit Parallel I/O Controllers multiplex the pins to/from these peripherals in order to reduce the device pin count, and peripheral DMA channels maximize the data throughput between these interfaces and the on- and off-chip memories. The AT91SAM9260 has a fully featured system controller for efficient system management, including a reset controller, shutdown controller, clock management, advanced interrupt controller (AIC), debug unit (DBGU), periodic interval timer, watchdog timer and real-time timer. It is available in a 217-ball LFBGA RoHS-compliant package and in a 208-pin Green QFP package. The AT91SAM9260 is supported by the AT91SAM9260 Evaluation Board and extensive third-party application development tools. It supports both Linux and Windows CE. It has been developed for highly connected image processing applications, such as point-of-sale terminals, Ethernet-based IP cameras, and bar code readers. AT91SAM9260 主要参数
- Status: Production
- SRAM (Bytes):2x4K
- Cache Memory (Byte):2x8K
- Ethernet MAC 10/10 :1
- Image Sensor Inter:1
- USB Host: 2xFS
- USB Device: FS
- USART/DBGU : 2/1
- 10-bit ADC Channel : 4
- Max. Clock Speed (:210
- I/O Pins :96
- In-System Programm :Y
- Enhanced USART : 1
- SDRAM Interface :1
- NAND Flash & E:1/1
- Peripheral DMA Cha :24
- Enhanced USART :4
- SPI:2
- TWI :1
- SSC:1
- 16-bit Timers :6
- Period Interval Ti :1
- Watchdog Timer:1
- RTC/RTT :-/1
- Power-On-Reset :2
- On-chip RC Oscilla :1
- Crystal Oscillator :2/2
- ARM Core :926EJ-S
- MMU/MPU : MMU
- High Current Pads :3
- I/O Voltage Domain :1.8/3.3
- Single Supply : N
- 绿色封装 :LFBGA 217 PQFP 208
AT91SAM9260 特性
- Incorporates the ARM926EJ-S? ARM? Thumb? Processor
– DSP Instruction Extensions, ARM Jazelle? Technology for Java? Acceleration
– 8-KByte Data Cache, 8-KByte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE?, Debug Communication Channel Support
- Additional Embedded Memories
– One 32 KByte Internal ROM, Single-cycle Access At Maximum Matrix Speed
– Two 4 KByte Internal SRAM, Single-cycle Access At Maximum Matrix Speed
- External Bus Interface (EBI)
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash?
- USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
- USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-lead PQFP
Package and Double Port in 217-ball LFBGA Package
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
- Ethernet MAC 10/100 Base T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
- Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
- Bus Matrix
– Six 32-bit-layer Matrix
– Boot Mode Select Option, Remap Command
- Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
- Reset Controller (RSTC)
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output
Control
- Clock Generator (CKGR)
– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on
Battery Backup Power Supply, Providing a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator, One up to 240 MHz PLL and One up to 130 MHz PLL
- Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
– Two Programmable External Clock Signals
- Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious
Interrupt Protected .
Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
- Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
- Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
- Real-time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
- One 4-channel 10-bit Analog-to-Digital Converter
- Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
– High-current Drive I/O Lines, Up to 16 mA Each
- Peripheral DMA Controller Channels (PDC)
- One Two-slot MultiMedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard? Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
- One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I2S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
- Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA? Infrared Modulation/Demodulation, Manchester Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Signal Control on USART0
- Two 2-wire UARTs
- Two Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications
- Two Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
- One Two-wire Interface (TWI)
– Master, Multi-master and Slave Mode Operation
– General Call Supported in Slave Mode
- IEEE? 1149.1 JTAG Boundary Scan on All Digital Pins
- Required Power Supplies:
– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
- Available in a 208-lead PQFP Green and a 217-ball LFBGA Green Package
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